1. Field of the Invention
The present invention relates to a voltage generating (output) circuit used as a drive source of a device for directly or indirectly driving a capacitive load; a common electrode drive circuit of a display device provided with the voltage generating circuit, for driving a common electrode in a display device; and a signal line drive circuit and a gray-scale (gradation) voltage generating circuit of a display device provided with the voltage generating circuit, for driving the signal lines in a display device.
2. Description of the Related Art
An active matrix liquid crystal display device of FIG. 48 represents an example of the above-mentioned display device. This liquid crystal display device includes liquid crystal which is a display medium between two substrates 100 and 101 facing each other. Pixel electrodes 103 (P(i, j)) are arranged in a matrix on the liquid crystal side of the substrate 100, and signal lines (data lines or source lines) 104 (S(1), S(2), . . . , S(i), . . . , S(N)) and scanning lines (gate lines) 105 (G(1), G(2), . . . , G(j), . . . , G(M)) are provided at the periphery of each pixel electrode 103 so as to cross each other. A thin film transistor (TFT) 102 (T(i, j)) is provided as a switching element in the vicinity of each crossing portion of the signal lines 104 and the scanning lines 105. The TFT 102 is connected to the signal line 104, the scanning line 105, and the pixel electrode 103 so as to drive the pixel electrode 103.
A common electrode 101a is provided on the liquid crystal side of the other substrate 101. A capacitance of the liquid crystal contributing to a display is formed between the common electrode 101a and the pixel electrodes 103.
A source driver (signal line drive circuit) 200 is connected to the signal lines 104, and a gate driver 300 is connected to the scanning lines 105. The source driver 200 supplies a voltage to the signal lines 104; in the example shown in FIG. 48, a digital source driver to which a video signal is applied in a digital form is used. The source driver 200 and the gate driver 300 are provided with an output signal from a control circuit 600. The control circuit 600 supplies a control signal POL to a gray-scale voltage generating circuit 400 and a common electrode drive circuit 500. The gray-scale voltage generating circuit 400 outputs gray-scale voltages v.sub.0, v.sub.1, v.sub.2, and v.sub.3 to the source driver 200, and the common electrode drive circuit 500 outputs a common electrode voltage v.sub.com to the common electrode 101a.
Hereinafter, the gray-scale voltage generating circuit 400 and the common electrode drive circuit 500 provided in the display device thus constructed will be as described. FIG. 49 shows an example of a drive circuit as proposed in "Drive Circuit for Display Apparatus," U.S. Pat. No. 5,402,142 to H. Okada et al. This drive circuit works as the gray-scale voltage generating circuit 400 as well as the common electrode drive circuit 500. The drive circuit is provided with an operational amplifier OP.sub.C for generating the common electrode voltage v.sub.com, and operational amplifiers OP.sub.0 to OP.sub.3 for generating the gray-scale voltages v.sub.0 to v.sub.3. Each inversion input terminal of the operational amplifiers OP.sub.C, OP.sub.0, and OP.sub.1 is provided with the control signal POL. The control signal POL is inverted by an inverter INV and then input to each inversion input terminal of the operational amplifiers OP.sub.2 and OP.sub.3. Each non-inversion input terminal of the operational amplifiers OP.sub.c and OP.sub.0 to OP.sub.3 is provided with an output from resistance type potential dividers PD.sub.com and PD.sub.0 to PD.sub.3, respectively. The resistance dividers PD.sub.com and PD.sub.0 to PD.sub.3 respectively consist of two fixed resistors R.sub.c1 and R.sub.c2, R.sub.01 and R.sub.02, R.sub.11 and R.sub.12, R.sub.21, and R.sub.22, and R.sub.31 and R.sub.32. One terminal of each of the resistors R.sub.c1, R.sub.01, R.sub.11, R.sub.21, and R.sub.31 is connected to a power supply V.sub.dd at a positive electric potential; and each of the other terminals of the resistors R.sub.c2, R.sub.02, R.sub.12, R.sub.22, and R.sub.32 is connected to a power supply V.sub.ss at a ground electric potential.
FIG. 50A shows an example of an output waveform of the above-mentioned drive circuit. When the control signal POL is at a high level, the common electrode voltage v.sub.com and the gray-scale voltages v.sub.0 to v.sub.3 are output so that a voltage applied to a pixel has a positive polarity with respect to the common electrode (a time period in this state is referred to as "positive time period"). When the control signal POL is at a low level, the common electrode voltage v.sub.com and the gray-scale voltages v.sub.0 to v.sub.3 are output so that a voltage applied to a pixel has a negative polarity with respect to the common electrode (a time period in this state is referred to as "negative time period"). In either time period, the absolute value of an electric potential difference between the common electrode and the pixel electrode is set to be higher in the same order of the data value 0 to 3 (i.e., .vertline.v.sub.0 -v.sub.com.vertline.&lt;.vertline.v.sub.1 -v.sub.com.vertline.&lt;.vertline.v.sub.2 -v.sub.com.vertline.&lt;.vertline.v.sub.3 -v.sub.com.vertline.).
The above relation represents a condition for driving a liquid crystal display body in a normally black mode. The above relation may be reversed when a liquid crystal display body is driven in a normally white mode. FIG. 50B shows an output in the case where the liquid crystal display body is driven in a normally white mode. It is not related to the present invention in which mode the liquid crystal display body is driven; therefore, in the following examples, either case (i.e., a normally black mode or a normally white mode) will be described. Unless otherwise stated, the level of a voltage refers to that in a positive time period. FIGS. 50A and 50B show waveforms in a line inversion in which the polarity of a voltage applied to a pixel is inverted per horizontal line (transverse line or row line).
The common electrode voltage v.sub.com and gray-scale voltages v.sub.0 to v.sub.3 oscillate in synchronization with the control signal POL based on a reference voltage v.sub.M (i.e., a voltage applied to each non-inversion input terminal) are output from the operational amplifiers OP.sub.c and OP.sub.0 to OP.sub.3 by appropriately setting the fixed resistors R.sub.01, R.sub.02, R.sub.11, R.sub.12, R.sub.21, R.sub.22, R.sub.31, and R.sub.32. As is understood from FIG. 50A, the voltages v.sub.com, v.sub.0, and v.sub.1 have a phase opposite to that of the voltages v.sub.2 and v.sub.3. The amplitude of these voltages are determined in terms of an amplification ratio of the operational amplifiers OP.sub.c and OP.sub.0 to OP.sub.3.
FIG. 51 shows the gray-scale voltages v.sub.0 to v.sub.3, based on the common electrode voltage v.sub.com which is applied to the common electrode 101a. As is understood from FIG. 51, when a certain pixel is selected by the gate driver 300 through the scanning lines 105, the pixel electrode 103 is charged with an output (i.e., one of the gray-scale voltages v.sub.0 to v.sub.3) from the source driver 200 connected to the selected pixel, and the difference between the electric potential at the pixel electrode 103 and that of the common electrode 101a facing the pixel electrode 103 with the liquid crystal layer sandwiched therebetween.
As described above, in the case where the common electrode 101a is driven with an A.C. voltage, there is an advantage that the amplitude of a voltage to be applied to a signal line for obtaining a predetermined voltage between the pixel electrode 103 and the common electrode 101a a can be decreased and a working voltage for the source driver 200 can be decreased (see Japanese Laid-Open Patent Publication No. 3-177890).
The gray-scale voltages v.sub.0 to v.sub.3 are supplied to the source driver 200 which is a signal line drive circuit.
FIG. 52 shows a circuit diagram showing the structure of the source driver 200. Video signal data is composed of two bits. That is, the video signal data has four values (0 to 3) and either of the gray-scale voltages v.sub.0 to v.sub.3 supplied from the gray-scale voltage generating circuit 400 shown in FIG. 48 is selected to be output in accordance with the respective value of the video signal data.
FIG. 53 shows a circuit diagram showing a circuit portion corresponding to the (i)th output. This circuit includes D-type flip-flops (sampling flip-flops) M.sub.SMP respectively for video signal data D.sub.0 and D.sub.1, flip-flops (holding flip-flops) M.sub.H respectively for the video signal data D.sub.0 and D.sub.1, a decoder DEC, analog switches ASW.sub.0 to ASW.sub.3 respectively provided between four kinds of power supplies V.sub.0 to V.sub.3 outputting gray-scale voltages v.sub.0 to v.sub.3, and a signal line S(i) ((i)th signal line 104). For sampling digital video signal data, various kinds of flip-flops other than D-type flip-flips can be used.
The operation of the source driver 200 with the above-mentioned structure will be described.
The two-bit video signal data (D.sub.0, D.sub.1) is taken in the sampling flip-flops M.sub.SMP at the time when a sampling pulse T.sub.SMPi corresponding to the (i)th signal line S(i) rises and held therein. When the sampling for one horizontal period is completed, an output pulse O.sub.E is given to the holding flip-flops M.sub.H and the video signal D.sub.0, D.sub.1 held in the sampling flip-flops M.sub.SMP are taken in the holding flip-flops M.sub.H to be output to the decoder DEC. The decoder DEC decodes the video signal data (D.sub.0, D.sub.1) and turns on one of the analog switches ASW.sub.0 to ASW.sub.3 in accordance with the values (0 to 3) of the video signal data (D.sub.0, D.sub.1), whereby one of the four gray-scale voltages v.sub.0 to v.sub.3 is output to the signal line S(i).
FIG. 54 shows a liquid crystal display device which receives video signal data composed of three bits (D.sub.0, D.sub.1, D.sub.2). FIG. 55 partially shows a circuit corresponding to the signal line S(i) of the source driver 210 of FIG. 54. More specifically, the source driver 210 has this structure as many as the signal lines 104 of a display panel (i.e., the number of this structure owned by the source driver 210 is identical with that of the signal lines 104 of a display panel). In this case, the video signal data has 8 values (0 to 7), and the signal voltage given to each pixel is either of eight levels of gray-scale voltages v.sub.0 to v.sub.7 output from gray-scale power supplies V.sub.0 to V.sub.7 of the gray-scale voltage generating circuit 410.
The source driver 210 includes first-stage D-type flip-flops M.sub.SMP used for sampling data, second-stage D-type flip-flops M.sub.H for holding data, a decoder DEC, and a plurality of analog switches ASW.sub.0 to ASW.sub.7 respectively provided between the eight external power supplies V.sub.0 to V.sub.7 and the signal line S(i). The first-stage D-type flip-flops M.sub.SMP and the second-stage D-type flip-flops M.sub.H are provided for each bit (D.sub.0, D.sub.1, V.sub.2). Eight kinds of gray-scale voltages v.sub.0 to v.sub.7 from the gray-scale voltage generating circuit 410 and control signals S.sub.0 to S.sub.7 from the decoder DEC are respectively input to the analog switches ASW.sub.0 to ASW.sub.7. The respective analog switches ASW.sub.0 to ASW.sub.7 are turned on to output the gray-scale voltages v.sub.0 to v.sub.7 in accordance with the levels of the control signals S.sub.0 to s.sub.7.
In the case where the value of the video signal data is 3 in the source driver 210, the analog switch ASW.sub.3 turns a conductive state, and the gray-scale voltage v.sub.3 is output. In this case, the gray-scale voltage v.sub.3 drives the signal line S(i) through the analog switch ASW.sub.3. The gray-scale voltage generating circuit 410 is provided separately from the source driver 210 constituting a drive circuit; thus, the gray-scale voltages v.sub.0 to v.sub.7 are input to a drive circuit for each signal line S(i). The reason for this is that the number of the actual drive circuits is identical with that of the signal lines 104. For example, the number of the signal lines 104 is 1920 in the case of the VGA liquid crystal display device. There is a possibility that the gray-scale voltage generating circuit 410 drives all of the signal lines 104 simultaneously. In such a case, it is difficult to produce the gray-scale voltage generating circuit 410, which is capable of sufficiently supplying an electric current required for driving all of the signal lines 104 simultaneously, with high integration on the chip identical with that of the source driver 210.
In addition, the source driver 210 has problems such as a complicated structure and a large size. The reason for this is as follows: In the case where the digital video signal is 4 bit, 16 kinds of gray-scale voltages are required; as the video signal increases to 6 bit, 8 bit, etc., the number of gray-scale voltages required increases to 64, 256, etc. That is to say, the gray-scale voltages whose number is the same as that of the gray scales are required. Because of this, the structure of the power supply circuit for forming such a number of gray-scale voltages becomes complicated and is enlarged, and moreover, the connecting line between the voltage generating circuit and the analog switches becomes complicated.
In the above-mentioned situation, conventionally, the source driver 210 is only used for a 3-bit or 4-bit video signal. Thus, when a video signal is composed of a large number of bits, a drive circuit for performing a gray-scale display has been difficult to construct.
Considering the above, the inventors of the present invention achieved a method for interpolating a gray scale between a plurality of gray-scale voltages given from outside and have filed applications (Japanese Patent Application No. 4-129164 and Japanese Laid-open Patent Publication Nos. 4-136983, 4-140787 and 5-53534).
FIG. 24 shows a liquid crystal display device 220 having a basic structure of the present invention, based on an oscillating voltage driving method proposed in U.S. Pat. No. 5,402,142, FIG. 25 is a block diagram corresponding to the signal line S(i) of the source driver of FIG. 24 per output. The following description refers to FIGS. 24 to 27 to which examples of the present invention (described later) will also refer to.
The case where video signal data is composed of 3 bits (D.sub.0, D.sub.1, D.sub.2) will be described. More specifically, the video signal data has 8 values (i.e., 0 to 7), and a signal voltage to be applied to each pixel is either one of external gray-scale voltages v.sub.0, v.sub.2, v.sub.5, and v.sub.7 supplied from the gray-scale power supplies V.sub.0 to V.sub.7 of a gray-scale voltage generating circuit 420, or either one of or a plurality of external gray-scale voltages between any two of the external gray-scale voltages v.sub.0, v.sub.2, v.sub.5, and v.sub.7.
A source driver 220 is provided for each bit (D.sub.0, D.sub.1, D.sub.2) of the video signal data. The source driver 220 includes first-stage D-type flip-flops M.sub.SMP for sampling, second-stage D-type flip-flops M.sub.H for holding, a selection control circuit SCOL, and analog switches ASW.sub.0 to ASW.sub.7 provided between the external gray-scale voltage power supplies V.sub.0 to V.sub.7 and a signal line S(i). The external gray-scale voltages v.sub.0, v.sub.2, v.sub.5, and v.sub.7 and control signals S.sub.0, S.sub.2, S.sub.5, and S.sub.7 from the selection control circuit SCOL are input to the analog switches ASW.sub.0, ASW.sub.2, ASW.sub.5, and ASW.sub.7. Further, a signal t.sub.3 having a predetermined duty ratio is supplied to the selection control circuit SCOL.
The source driver 220 shown in FIGS. 24 and 25 has the same effects as those of the source driver 210 shown in FIGS. 54 and 55 in terms of the realization of an 8-gray-scale display. In the source driver of FIG. 25, in order to realize the 8-gray-scale display, the number of external gray-scale power supplies is reduced to four (i.e., half of the conventional example shown in FIG. 55). In the source driver 220, the outputs from the gray-scale voltage power supplies V.sub.1, V.sub.3, V.sub.4, and V.sub.6 are formed by the above-mentioned oscillating voltage driving method.
Table 1 shows the relation between the video signal data input to the source driver 3 and the gray-scale voltage obtained from the source driver 3.
TABLE 1 Output S(i) Output S(i) d.sub.2 d.sub.1 d.sub.0 (FIG. 55) (FIG. 25) 0 0 0 V0 V0 0 0 1 V1 ##EQU1## 0 1 0 V2 V2 0 1 1 V3 ##EQU2## 1 0 0 V4 ##EQU3## 1 0 1 V5 V5 1 1 0 V6 ##EQU4## 1 1 1 V7 V7
When the value of the video signal data is either of 1, 2, 5, or 7, one of the external gray-scale voltages v.sub.0 to v.sub.7 input from outside is output to the signal line S(i). When the value of the video signal data is other than 1, 2, 5, and 7, an oscillating voltage oscillating between any two external gray-scale voltages v.sub.0 to v.sub.7 are output to the signal line S(i). Thus, an 8-gray-scale display can be obtained from 4 external gray-scale voltages.
Hereinafter, the oscillating voltage driving method will be described.
The output waveform corresponding to the external gray-scale voltage v.sub.1 is shown in (1) of FIG. 26, and the output waveform corresponding to the external gray-scale voltages v.sub.0 and v.sub.2 are shown in (2) of FIG. 26. For example, an oscillating voltage oscillating a plurality of times between the external gray-scale voltages v.sub.0 and v.sub.2 during one output period (e.g., one horizontal scanning period) is output. The resistance and capacitance of wirings (i.e., signal line) between the source driver 220 and pixels forming a display panel constitutes a low pass filter (LPF), as shown in FIG. 56. The oscillating voltage passes through the LPF, whereby the gray-scale voltage v.sub.1 is applied to a pixel as an average value of the oscillating voltage.
FIG. 27 shows the waveform of the external gray-scale voltages v.sub.0 and v.sub.7 together with a common electrode signal v.sub.com. FIG. 27 shows the waveforms in the case of line inversion in which the polarity of the voltage is inverted per horizontal scanning period. Hereinafter, the case of the line inversion will be described.
As is understood from FIG. 27, the external gray-scale voltage v.sub.0 has a polarity opposite to that of the common electrode signal v.sub.com, and the external gray-scale voltage v.sub.0 and the common electrode signal v.sub.com have rectangular waveforms which are alternately inverted at an identical point. In the case where the video signal data is 0, the capacitance of the liquid crystal layer of each pixel and the like is charged with a voltage between the gray-scale voltage v.sub.0 and the common electrode signal v.sub.com.
As described above, the signal line 104 of the display panel is charged and discharged between a positive electric potential and a negative electric potential each time the outputs of the common electrode drive power supply 500 and the gray-scale generating circuit 420 have their polarity inverted. FIG. 56 shows an equivalent circuit in the case where the signal line 104 is considered as a load. In this equivalent circuit, an equivalent resistor R.sub.s of the signal line 104 and an equivalent capacitance C.sub.s thereof are connected in series. In a practical liquid crystal display device, the number of the signal lines 104 are 1920 (640.times.3), for example, in a display panel with a VGA specification, and the gray-scale power supplies are in some cases required to drive a load 1920 times that of the circuit shown in FIG. 56.
Hereinafter, a peak electric current flowing when the polarity of the gray-scale voltage is inverted will be considered.
Assuming that the resistance of the equivalent resistor R.sub.s of the signal line 104 is 50 K.OMEGA. and the maximum electric potential difference between the positive state and the negative state in the common electrode 101a is 10 V, the maximum peak electric current is 10/50 K.OMEGA..times.1920=384 mA. Conventionally, the gray-scale power supply is required to have an ability of charging the maximum capacity of an electric current; therefore the gray-scale power supply may have a structure as shown in FIG. 57.
This circuit includes an operational amplifier OP and a complementary circuit (electric current amplifier) BUF. The operational amplifier OP is provided with a predetermined voltage and a control voltage POL. The output terminal of the operational amplifier OP is connected the complementary circuit BUF consisting of transistors Q.sub.1 and Q.sub.2. When an output voltage V.sub.out from the complementary circuit BUF is fed back to the operational amplifier OP, the operational amplifier OP performs an inversion amplification. In the circuit of FIG. 57, the operational amplifier OP uses a slewing rate and an electric current capacity as large as possible.
The above-mentioned art causes the increase in cost. In addition, since the complementary circuit BUF (transistors Q.sub.1 and Q.sub.2) itself consumes an electric power, the consumption of electric current is increased. The increase in the consumption of electric current means an increase in electric current which is not required for driving the display panel.
There is no substantial difference between the case where the circuit shown in FIG. 57 is used as the common electrode drive circuit and the case where the circuit shown in FIG. 57 is used for each gray-scale voltage generating element of the gray-scale voltage generating circuit. However, in the case where the circuit shown in FIG. 57 is used for each gray-scale voltage generating element, the output voltage will have an amplitude and a center voltage corresponding to the respective data and will have the same phase with respect to the control voltage POL.
Further, there is another problem. That is, in the conventional gray-scale voltage generating device, when the signal line drive circuit (source driver) selects either of the gray-scale voltages v.sub.0 to v.sub.3, a load is rapidly fluctuated at the time of switching the polarity of the output of the gray-scale voltage generating circuit. In the case where the oscillating voltage driving method is applied to the signal line drive circuit, the load fluctuation is larger and the change speed thereof is higher than the case where a gray-scale voltage is merely selected.
Such a load fluctuation causes the fluctuation of the output voltage. FIG. 58 shows an example of an output waveform of a certain voltage level of the gray-scale voltage generating circuit, in the case where the oscillating voltage driving method is applied to the signal line drive circuit. As shown in this figure, since the voltage having the output waveform of the gray-scale voltage generating circuit is fluctuated, the voltage to be charged to a pixel is not uniform, resulting in the deterioration of display quality.
In order to solve the above-mentioned problems, it is considered that a capacitor be provided between the output terminal of the gray-scale voltage generating circuit and the gray-scale voltage input terminal of the signal line drive circuit, thereby absorbing and supplying a charge in accordance with the voltage fluctuation. However, in this case, it has been difficult to use a capacitor with a sufficient capacitance. The reasons for this are as follows:
When the output terminal of the gray-scale voltage generating circuit is connected to the capacitor, the capacitor itself becomes a load on the gray-scale voltage generating circuit performing an A.C. drive. This necessitates that the capacitor be charged and discharged by the gray-scale voltage generating circuit at the time of switching the polarity of the gray-scale voltage. As a result, there arises some problems such as the delayed output waveform of the gray-scale voltage generating circuit and the increased electric power consumption is increased. Thus, in actuality, it has been impossible to use a capacitor with a sufficient capacitance.
The above-mentioned problems are hardly ever known in the case where the source driver 210 having a structure shown in FIG. 55 is used; however, these problems are serious in the case of the signal line drive circuit using the oscillating voltage driving method as shown in FIG. 25. More specifically, a capacitor with a capacitance sufficient for compensating the current fluctuation due to the oscillating voltage which is switched at a higher speed per output period cannot be used. This causes the strain of the voltage as shown in FIG. 58 and in some cases, the deterioration of a display will be caused. In addition, in the common electrode driving circuit, the problems similar to those in the gray-scale voltage generating circuit arise. The voltage (output waveform) from the common electrode driving circuit is fluctuated because of the sudden load fluctuation of the source driver 220, in particular, using the oscillating voltage driving method; as a result, a display quality is deteriorated.